APPENDIX
3.3 Notes on use
3.3.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 3A16)
•Timer XY mode register (address 2316)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.3.1 Sequence of changing relevant register
s Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt edge selection register (address 3A16)
3850 Group (Spec. H) User’s Manual
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