AD807A-155BRRL(RevB) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD807A-155BRRL
(Rev.:RevB)

Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming

Analog Devices 

AD807

30

TEST CONDITIONS

WORST-CASE:

–40؇C, 4.5V

25

20

15

10

5

0

1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3

RMS JITTER – Degrees

TPC 7. Output Jitter Histogram

1E+3

100E+0

10E+0

AD807

XFCB’s dielectric isolation allows the different blocks within

this mixed-signal IC to be isolated from each other, hence the

2 mV Sensitivity is achieved. Traditionally, high speed compara-

tors are plagued by crosstalk between outputs and inputs, often

resulting in oscillations when the input signal approaches 10 mV.

The AD807 quantizer toggles at ± 650 µV (1.3 mV sensitivity) at

the input without making bit errors. When the input signal is

lowered below ± 650 µV, circuit performance is dominated by

input noise, and not crosstalk.

PIN 13

0.1␮F 500⍀

NIN 12

QUANTIZER

0.1␮F 500⍀ INPUT

OPTIONAL FILTER

AD807

50⍀

50⍀

309⍀

FERRITE BEAD

3.65k⍀

0.1␮F

0.1␮F

AVCC2 14

0.1␮F

AVCC1 11

0.1␮F

10␮F

0.1␮F

50⍀

311MHz

NOISE

INPUT

+5V CHOKE

“BIAS TEE”

VCC1 6

0.1␮F

VCC2 3

0.1␮F

Figure 6. Power Supply Noise Sensitivity Test Circuit

1E+0

SONET MASK

100E–3

10E+0

100E+0

1E+3 10E+3 100E+3

FREQUENCY – Hz

TPC 8. Jitter Tolerance

1E+6

10E+6

3.0

PSR – NO FILTER

2.0

PIN 13

NIN 12

0.1␮F 500⍀

QUANTIZER

0.1␮F 500⍀ INPUT

AD807

50⍀ 50⍀

3.65k⍀

AVCC2 14

0.1␮F

AVCC1 11

0.1␮F

309⍀

0.1␮F

0.1␮F

CHOKE

“BIAS TEE”

50⍀

+5V

10␮F

VCC1 6

0.1␮F

VCC2 3

0.1␮F

311MHz

NOISE

INPUT

CMR

1.0

PSR – WITH FILTER

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

NOISE – V p-p @ 311MHz

TPC 9. Output Jitter vs. Supply Noise and

Output Jitter vs. Common Mode Noise

THEORY OF OPERATION

Quantizer

The quantizer (comparator) has three gain stages, providing a

net gain of 350. The quantizer takes full advantage of the Extra

Fast Complementary Bipolar (XFCB) process. The input stage

uses a folded cascode architecture to virtually eliminate pulse

width distortion, and to handle input signals with common-

mode voltage as high as the positive supply. The input offset

voltage is factory trimmed and guaranteed to be less than 500 µV.

Figure 7. Common-Mode Rejection Test Circuit

Signal Detect

The input to the signal detect circuit is taken from the first stage

of the quantizer. The input signal is first processed through a gain

stage. The output from the gain stage is fed to both a positive

and a negative peak detector. The threshold value is subtracted

from the positive peak signal and added to the negative peak signal.

The positive and negative peak signals are then compared. If the

positive peak, POS, is more positive than the negative peak,

NEG, the signal amplitude is greater than the threshold, and the

output, SDOUT, will indicate the presence of signal by remain-

ing low. When POS becomes more negative than NEG, the

signal amplitude has fallen below the threshold, and SDOUT

will indicate a loss of signal (LOS) by going high. The circuit

provides hysteresis by adjusting the threshold level higher by a

factor of two when the low signal level is detected. This means

that the input data amplitude needs to reach twice the set LOS

threshold before SDOUT will signal that the data is again valid.

This corresponds to a 3 dB optical hysteresis.

REV. B

–7–

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