M38005M2FS View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
Manufacturer
M38005M2FS Datasheet PDF : 173 Pages
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HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt Request
(Note 1)
Store Return Address
on Stack (Note 2)
M(S) ← (PCH)
(S) ← (S – 1)
M(S) ← (PCL)
(S) ← (S – 1)
Subroutine
Restore Return
Address
Execute RTS
(S) ← (S + 1)
(PCL) ← M(S)
(S) ← (S + 1)
(PCH) ← M(S)
Execute JSR
M(S) ← (PCH)
(S) ← (S – 1)
M(S) ← (PCL)
(S) ← (S – 1)
M(S) ← (PS)
(S) ← (S – 1)
Interrupt
Service Routine
Execute RTI
(S) ← (S + 1)
(PS) ← M(S)
(S) ← (S + 1)
(PCL) ← M(S)
(S) ← (S + 1)
(PCH) ← M(S)
Store Return Address
on Stack (Note 2)
Store Contents of
Processor Status
Register on Stack
I Flag “0” to “1”
Fetch the Jump
Vector
Restore Contents of
Processor Status
Register
Restore Return
Address
Notes 1 : The condition to enable the interrup t → Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 4. Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
PHA
Processor status register
PHP
Pop instruction from stack
PLA
PLP
3800 GROUP USER’S MANUAL
1-11
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