PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

SLEEP

Enter SLEEP mode

Syntax:

[ label ] SLEEP

Operands:

None

Operation:

00h → WDT,

0 → WDT postscaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding:

0000 0000 0000 0011

Description:

The power-down status bit (PD) is

cleared. The time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words:

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

Process

Data

Go to

sleep

Example:

SLEEP

Before Instruction

TO = ?

PD = ?

After Instruction

TO = 1 †

PD = 0

† If WDT causes wake-up, this bit is cleared.

SUBFWB

Subtract f from WREG with borrow

Syntax:

[ label ] SUBFWB f [ ,d [,a] ]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(WREG) – (f) – (C) → dest

Status Affected: N,OV, C, DC, Z

Encoding:

0101 01da ffff ffff

Description:

Subtract register 'f' and carry flag

(borrow) from WREG (2’s comple-

ment method). If 'd' is 0, the result

is stored in WREG. If 'd' is 1, the

result is stored in register 'f'

(default) . If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, the Bank

will be selected as per the BSR

value.

Words:

1

Cycles:

1

Q Cycle Activity:

Q1

Decode

Q2

Read

register ’f’

Q3

Process

Data

Q4

Write to

destination

DS41142A-page 130

Preliminary

 2001 Microchip Technology Inc.

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