PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

12.3.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-

tion of a SLEEP instruction, the SLEEP instruction

will complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the TO bit will

not be set and PD bits will not be cleared.

• If the interrupt condition occurs during or after

the execution of a SLEEP instruction, the device

will immediately wake-up from SLEEP. The

SLEEP instruction will be completely executed

before the wake-up. Therefore, the WDT and

WDT postscaler will be cleared, the TO bit will be

set and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

12.3.3 TWO-SPEED CLOCK START-UP

When using an external clock source, wake-up from

SLEEP causes a unique start-up procedure. The inter-

nal oscillator starts immediately upon wake-up, while

the external source is stabilizing. Once the Oscillator

Start-up Time-out (OST) is complete, the clock source

is switched to the external clock. The result is nearly

immediate code execution upon wake-up. Refer to

Section 2.6.

FIGURE 12-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

OSC1

CLKOUT(4)

INT pin

INTF Flag

(INTCON<1>)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

TOST(2)

Interrupt Latency(3)

GIEH bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC

Instruction

Fetched

Instruction

Executed

Inst(PC) = SLEEP

Inst(PC - 1)

PC+2

Inst(PC + 2)

SLEEP

Processor in

SLEEP

PC+4

PC+4

Inst(PC + 4)

Inst(PC + 2)

PC + 4

Dummy cycle

0008h

Inst(0008h)

Dummy cycle

000Ah

Inst(000Ah)

Inst(0008h)

Note 1: XT, HS or LP oscillator mode assumed.

2: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.

3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for external RC oscillator, EC osc, and INTOSC modes.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 91

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