PIC16C925/926
FIGURE 5-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Instruction
Fetched
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC+6
TMR0
T0
Instruction
Executed
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0
executed
Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
reads NT0
reads NT0
reads NT0
reads NT0 + 1 reads NT0 + 2
FIGURE 5-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Instruction
Fetched
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC+6
TMR0
T0
T0+1
NT0
NT0+1
PC+6
Instruction
Executed
Write TMR0
executed
Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
reads NT0
reads NT0 reads NT0
reads NT0
reads NT0 + 1
FIGURE 5-4:
TIMER0 INTERRUPT TIMING
OSC1
CLKOUT(3)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0
FEh
FFh
00h
01h
02h
1
1
TMR0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
Inst (PC)
Inst (PC-1)
PC +1
Inst (PC+1)
Inst (PC)
PC +1
Dummy cycle
0004h
Inst (0004h)
Dummy cycle
0005h
Inst (0005h)
Inst (0004h)
Note 1: Interrupt flag bit TMR0IF is sampled here (every Q1).
2: Interrupt latency = 4TCY where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS39544A-page 42
Preliminary
2001 Microchip Technology Inc.