PIC16C926-PT View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C926-PT

64/68-Pin CMOS Microcontrollers with LCD Driver

Microchip Technology 

PIC16C925/926

6.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

6.2 Timer1 Operation in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode, the timer increments on every rising edge of

clock input on pin RC1/T1OSI when bit T1OSCEN is

set, or pin RC0/T1OSO/T1CKI when bit T1OSCEN is

cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The pres-

caler is an asynchronous ripple counter.

In this configuration, during SLEEP mode, Timer1 will

not increment even if the external clock is present,

since the synchronization circuit is shut-off. The pres-

caler however will continue to increment.

6.2.1

EXTERNAL CLOCK INPUT TIMING

FOR SYNCHRONIZED COUNTER

MODE

When an external clock input is used for Timer1 in Syn-

chronized Counter mode, it must meet certain require-

ments. The external clock requirement is due to

internal phase clock (TOSC) synchronization. Also,

there is a delay in the actual incrementing of TMR1

after synchronization.

When the prescaler is 1:1, the external clock input is

the same as the prescaler output. The synchronization

of T1CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2TOSC (and

a small RC delay of 20 ns), and low for at least 2TOSC

(and a small RC delay of 20 ns). Refer to the appropri-

ate electrical specifications, parameters 45, 46, and 47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous ripple

counter type prescaler, so that the prescaler output is

symmetrical. In order for the external clock to meet the

sampling requirement, the ripple counter must be taken

into account. Therefore, it is necessary for T1CKI to

have a period of at least 4TOSC (and a small RC delay

of 40 ns), divided by the prescaler value. The only

requirement on T1CKI high and low time is that they do

not violate the minimum pulse width requirements of

10 ns). Refer to the appropriate electrical specifica-

tions, parameters 40, 42, 45, 46, and 47.

FIGURE 6-1:

TIMER1 BLOCK DIAGRAM

Set Flag bit

TMR1IF on

Overflow

RC0/T1OSO/T1CKI

RC1/T1OSI

TMR1

0

Synchronized

Clock Input

TMR1H TMR1L

1

T1OSC

TMR1ON

On/Off

T1SYNC

T1OSCEN FOSC/4

Enable

Oscillator(1)

Internal

Clock

1

Prescaler

1, 2, 4, 8

0

2

T1CKPS1:T1CKPS0

Synchronize

det

SLEEP Input

TMR1CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS39544A-page 48

Preliminary

 2001 Microchip Technology Inc.

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