PIC16LC926-I/PT View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC926-I/PT Datasheet PDF : 182 Pages
| |||
PIC16C925/926
10.3 Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN<4:0>
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
10.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started. After
this, the GO/DONE bit can be set to start the
conversion.
In Figure 10-3, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 10-3:
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
A 2TAD wait is necessary before the next
acquisition is started.
10.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general pur-
pose 8-bit registers.
DS39544A-page 80
Preliminary
2001 Microchip Technology Inc.
Share Link: 