ST62E09CD6/SWD View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62E09CD6/SWD

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

5.3 RESET

5.3.1 Introduction

The MCU can be reset in three ways:

s A low pulse input on the RESET pin

s Internal Watchdog reset

s Internal Low Voltage Detector (LVD) reset

5.3.2 RESET sequence

The basic RESET sequence consists of 3 main

phases:

s Internal (watchdog or LVD) or external Reset

event

s A delay of 2048 clock (fINT) cycles

s RESET vector fetch

The 2048 clock cycle delay allows the oscillator to

stabilise and ensures that recovery has taken

place from the Reset state.

Figure 13. RESET Sequence

VDD

VIT+

VIT-

The RESET vector fetch phase duration is 2 clock

cycles.

When a reset occurs:

– The stack is cleared

– The PC is loaded with the address of the Reset

vector. It is located in program ROM starting at

address 0FFEh.

A jump to the beginning of the user program must

be coded at this address.

– The interrupt flag is automatically set, so that the

CPU is in Non Maskable Interrupt mode. This

prevents the initialization routine from being in-

terrupted. The initialization routine should there-

fore be terminated by a RETI instruction, in order

to go back to normal mode.

WATCHDOG

RESET

LVD

RESET

WATCHDOG UNDERFLOW

RESET PIN

INT ERNAL

RESET

RUN

RESET

RUN

RUN

RESET

RESET

RUN

2048 CLOCK CYCLE (fINT) DELAY

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