ST16 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST16

CHIP SET INTERFACE SPECIFICATION

STMicroelectronics 

ST16-19RFRDCS

FSD_CHIPSET_B/0104VP2

1.6.2 Status register

The mapping of the different state bits is given by the following table:

Table 3 : Reception status register description

"Address

’0

"Description

Reception Control

bit [1:0]: Rx_Speed_Value "00" = 106K

"01" = 212K

"10" & "11"= 424K

bit 2:

Rx_CRC_OK

’0’ = CRC OK

’1’ = CRC Wrong

bit 3:

Rx_EGT_TooLong ‘0' = EGT OK

'1' = EGT too long

bit 4: Rx_Bad_StopBit

‘0' = Stop Bit Value OK '1' = Stop Bit wrong => frame wrong?

bit 5:

ST Reserved => read at '0'

bit 6:

ST Reserved => read at '0'

bit 7:

ST Reserved => read at '0'

1.7 FPGA PIN-OUT & CHIP SET BLOCK DIAGRAM

The FPGA pin-out is given by the list below:

Table 4 : FPGA pin out

Signal

clk1356

mic_ctrl_ndata

mic_data<0>

mic_data<1>

mic_data<2>

mic_data<3>

mic_data<4>

mic_data<5>

mic_data<6>

mic_data<7>

mic_r_nw

mic_strb_b

reset

rx_bpsk_in

rx_fifo_empty

rx_irq_eof

rx_valid

tx_fifo_empty

tx_start

tx_streamout

Site

P2

P176

P184

P185

P186

P187

P188

P189

P190

P191

P181

P179

P102

P48

P89

P180

P198

P29

P30

P37

8/15

Share Link: