ST72652 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72652 Datasheet PDF : 166 Pages
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ST7265x
PWM/BRM GENERATOR (Cont’d)
Figure 58. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
11.5.4 Register Description
On a channel basis, the 10 bits are separated into
two data registers:
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
PULSE BINARY WEIGHT REGISTERS (PWMi)
Read / Write
Reset Value 1000 0000 (80h)
7
0
1 POL P5 P4 P3
P2
P1
P0
Bit 7 = Reserved (Forced by hardware to “1”)
BRM REGISTERS
Read / Write
Reset Value: 0000 0000 (00h)
7
0
B7 B6 B5 B4 B3
B2
B1
B0
These registers define the intervals where an in-
cremental pulse is added to the beginning of the
original PWM pulse. Two BRM channel values
share the same register.
Bit 7:4 = B[7:4] BRM Bits (channel i+1).
Bit 3:0 = B[3:0] BRM Bits (channel i)
Bit 6 = POL Polarity Bit for channel i.
0: The channel i outputs a “1” level during the bina-
ry pulse and a “0” level after.
1: The channel i outputs a “0” level during the bina-
ry pulse and a “1” level after.
Note: From the programmer's point of view, the
PWM and BRM registers can be regarded as be-
ing combined to give one data value.
Bit 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i.
This register contains the binary value of the pulse.
For example :
1
POL
P
P
P
P
P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
1
POL
P
P
P
P
P
P
B
B
B
B
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