ADSP-21060LCB-133 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21060LCB-133

SHARC Processor

Analog Devices 

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

TRANSMIT

CLKIN

LCLK 1x

OR

LCLK 2x

tDLCLK

tLCLKTWH

tLCLKTWL

tDLDCH

tHLDCH

LAST NIBBLE

TRANSMITTED

FIRST NIBBLE

TRANSMITTED

LCLK INACTIVE

(HIGH)

LDAT(3:0)

LACK (IN)

OUT

tSLACH

tHLACH

tDLACLK

RECEIVE

THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

CLKIN

LCLK 1x

OR

LCLK 2x

L DAT (3 :0)

LACK (OUT)

tD LAHC

tLCLKRWH

tLCLKIW

tSLDCL

IN

tHLDCL

tLCLKRWL

tDLALC

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

CLKIN

LCLK

LDAT(3:0)

LACK

tENDLK

t TDLK

LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

LINK PORT INTERRUPT SETUP TIME

CLKIN

LCLK

LACK

tSLCK

t HLCK

Figure 24. Link Ports—Receive

Rev. F | Page 41 of 64 | March 2008

Share Link: