STPCI2HEYC(2002) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2HEYC
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

STRAP OPTION

3.1.4. STRAP REGISTER 2

This register is read only with the exception of bit 4

STRAP2

Access = 0022h/0023h

Regoffset =04Ch

7

6

5

4

3

2

1

0

MD[53]

MD[52]

RSV

MD[20]

MD[19]

MD[18]

MD[51]

MD[50]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

MD[53]

MD[52]

Rsv

MD[20]

MD[19]

MD[18]

MD[51]

MD[50]

Description

This bit reflects the value sampled on MD[53] pin and determines

whether the internal Parallel Port Controller is used

0: Internal Parallel Port Controller is disabled

1: Internal Parallel Port Controller is enabled

This bit reflects the value sampled on MD[52] pin and determines

whether the internal Keyboard controller is used

0: Internal Keyboard Controller is disabled

1: Internal Keyboard Controller is enabled

Reserved

This bit reflects the value sampled on MD[20] pin and controls the Dot

clock pin (DCLK) direction as follows:

0: Input.

1: Output of the internal frequency synthesizer DCLK PLL.

This bit reflects the value sampled on MD[19] pin and controls the

Memory clock output pin (MCLKO) as follows:

0: Tristated.

1: Output of the internal frequency synthesizer MCLKO PLL.

This bit reflects the value sampled on MD[18] pin and controls the Host

clock pin (HCLK) direction as follows:

0: Input.

1: Output of the internal frequency synthesizer HCLK PLL.

This bit reflects the value sampled on MD[51] pin and determines

whether the internal UART1 is enabled:

0: Internal UART1 is disabled

1: Internal UART1 is enabled

This bit reflects the value sampled on MD[50] pin and determines

whether the internal UART2 is enabled:

0: Internal UART2 is disabled

1: Internal UART2 is enabled

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Issue 1.0 - July 24, 2002

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