STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

IOCHRDY IO Channel Ready. IOCHRDY is the IO MCS16# Memory Chip Select16. This is the

channel ready signal of the ISA bus and is driven decode of LA23-17 address pins of the ISA

as an output in response to an ISA master cycle address bus without any qualification of the

targeted to the host bus or an internal register of command signal lines. MCS16# is always an

the STPC Atlas. The STPC Atlas monitors this input. The STPC Atlas ignores this signal during

signal as an input when performing an ISA cycle IO and refresh cycles.

on behalf of the host CPU, DMA master or refresh.

ISA masters which do not monitor IOCHRDY are IOCS16# IO Chip Select16. This signal is the

not guaranteed to work with the STPC Atlas since decode of SA15-0 address pins of the ISA address

the access to the system memory can be bus without any qualification of the command

considerably delayed due to CRT refresh or a signals. The STPC Atlas does not drive IOCS16#

write back cycle.

(similar to PC-AT design). An ISA master access

to an internal register of the STPC Atlas is

ALE Address Latch Enable. This is the address executed as an extended 8-bit IO cycle.

latch enable output of the ISA bus and is asserted

by the STPC Atlas to indicate that LA23-17, SA19- REF# Refresh Cycle. This is the refresh command

0, AEN and SBHE# signals are valid. The ALE is signal of the ISA bus. It is driven as an output

driven high during refresh, DMA master or an ISA when the STPC Atlas performs a refresh cycle on

master cycles by the STPC Atlas.

the ISA bus. It is used as an input when an ISA

ALE is driven low after reset.

t(s) BHE# System Bus High Enable. This signal, when

asserted, indicates that a data Byte is being

c transferred on SD15-8 lines. It is used as an input

u when an ISA master owns the bus and is an output

d at all other times.

ro MEMR# Memory Read. This is the memory read

P command signal of the ISA bus. It is used as an

te input when an ISA master owns the bus and is an

output at all other times.

le The MEMR# signal is active during refresh.

so MEMW# Memory Write. This is the memory write

b command signal of the ISA bus. It is used as an

O input when an ISA master owns the bus and is an

- output at all other times.

t(s) SMEMR# System Memory Read. The STPC Atlas

generates SMEMR# signal of the ISA bus only

c when the address is below one MByte or the cycle

u is a refresh cycle.

rod SMEMW# System Memory Write. The STPC Atlas

generates SMEMW# signal of the ISA bus only

P when the address is below one MByte.

te IOR# I/O Read. This is the IO read command

le signal of the ISA bus. It is an input when an ISA

o master owns the bus and is an output at all other

s times.

ObIOW# I/O Write. This is the IO write command

master owns the bus and is used to trigger a

refresh cycle.

The STPC Atlas performs a pseudo hidden

refresh. It requests the host bus for two host clocks

to drive the refresh address and capture it in

external buffers. The host bus is then relinquished

while the refresh cycle continues on the ISA bus.

AEN Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to

indicate that a DMA transfer will occur. The

enabling of the signal indicates to IO devices to

ignore the IOR#/IOW# signal during DMA

transfers.

IOCHCK# IO Channel Check. IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal

becomes active upon seeing IOCHCK# active if

the corresponding bit in Port B is enabled.

GPIOCS# I/O General Purpose Chip Select 1.

This output signal is used by the external latch on

ISA bus to latch the data on the SD[7:0] bus. The

latch can be use by PMU unit to control the

external peripheral devices to power down or any

other desired function.

RTCRW# Real Time Clock RW#. This pin is used

as RTCRW#. This signal is asserted for any I/O

write to port 71h.

RTCDS# Real Time Clock DS. This pin is used as

RTCDS#. This signal is asserted for any I/O read

signal of the ISA bus. It is an input when an ISA to port 71h. Its polarity complies with the DS pin of

master owns the bus and is an output at all other the MT48T86 RTC device when configured with

times.

Intel timings.

MASTER# Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

RTCAS Real time clock address strobe. This

signal is asserted for any I/O write to port 70h.

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