STPCI2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STPCI2 Datasheet PDF : 108 Pages
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STPC® ATLAS
3.1.3 HCLK PLL STRAP REGISTER
This register is read only.
HCLK_STRAP0
7
RSV
Access = 0022h/0023h
Regoffset =05Fh
6
5
4
3
2
1
0
MD[26]
MD[25]
MD[24]
RSV
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-6
Rsv
These bits are fixed to ‘0’
Bits 5-3
MD[26:24]
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in Table 3-1
Bits 2-0
uct(s) MD[3]
rod 0
0
P 0
Obsolete Product(s) - Obsolete 0
Rsv
Reserved
Table 3-1. HCLK Frequency Configuration
MD[2]
0
0
0
0
MD[26]
MD[25]
0
0
0
0
0
1
0
1
All other settings are reserved
MD[24]
0
1
0
1
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
40/108
1
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