STPCI2GDYI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2GDYI

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

6.3.1. POWER DECOUPLING

An appropriate decoupling of the various STPC

power pins is mandatory for optimum behaviour.

When insufficient, the integrity of the signals is

deteriorated, the stability of the system is reduced

and EMC is increased.

minimum. The use of multiple capacitances with

values in decade is the best (for example: 10pF,

1nF, 100nF, 10uF), the smallest value, the closest

to the power pin. Connecting the various digital

power planes through capacitances will reduce

furthermore the overall impedance and electrical

noise.

6.3.1.1. PLL decoupling

6.3.2. 14MHZ OSCILLATOR STAGE

This is the most important as the STPC clocks are The 14.31818 MHz oscillator stage can be

generated from a single 14MHz stage using implemented using a quartz, which is the preferred

multiple PLLs which are highly sensitive analog and cheaper solution, or using an external 3.3V

cells. The frequencies to filter are the 25-50 KHz oscillator.

range which correspond to the internal loop

bandwidth of the PLL and the 10 to 100 MHz The crystal must be used in its series-cut

frequency of the output. PLL power pins can be fundamental mode and not in overtone mode. It

tied together to simplify the board layout.

must have an Equivalent Series Resistance (ESR,

Figure 6-3. PLL decoupling

ct(s) VDD_PLL

PWR

Produ VSS_PLL

100nF 47uF

te GND

le Connections must be as short as possible

bso 6.3.1.2. Decoupling of 3.3V and Vcore

O A power plane for each of these supplies with one

- decoupling capacitance for each power pin is the

t(s) Figure 6-4. 14.31818 MHz stage

sometimes referred to as Rm) of less than 50

Ohms (typically 8 Ohms) and a shunt capacitance

(Co) of less than 7 pF. The balance capacitors of

16 pF must be added, one connected to each pin,

as described in Figure 6-4.

In the event of an external oscillator providing the

master clock signal to the STPC device, the

LVTTL signal should be connected to XTALI, as

described in Figure 6-4.

As this clock is the reference for all the other on-

chip generated clocks, it is strongly

recommended to shield this stage, including the

2 wires going to the STPC balls, in order to reduce

the jitter to the minimum and reach the optimum

system stability.

duc XTALI

XTALO

Pro1MOHM

XTALI

XTALO

3.3V

Obsolete 15pF

15pF

76/108

1

Share Link: