STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

6.3.4. PCI BUS

The PCI bus is always active and the following

control signals must be pulled-up to 3.3V or 5V

through 8K2 resistors even if this bus is not

connected to an external device: FRAME#,

TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,

SERR#, PERR#, PCI_REQ#[2:0].

Figure 6-8. Typical PCI clock routing

PCI_CLKO must be connected to PCI_CLKI

through a 10 to 33 Ohms resistor. Figure 6-8

shows a typical implementation.

For more information on layout constraints, go to

the place and route recommendations section.

PCICLKI

0 - 33pF

t(s) PCICLKO

uc 0 - 22

10 - 33

PCICLKA

PCICLKB

PCICLKC

Device A

Device B

Device C

Prod In the case of higher clock load it is recommended

te to use a zero-delay clock buffer as described in

le Figure 6-9. This approach is also recommended

when implementing the delay on PCICLKI

according to the PCI section of the Electrical

Specifications chapter.

o Figure 6-9. PCI clock routing with zero-delay clock buffer

) - Obs PCICLKI

Obsolete Product(s PCICLKO

PLL

Device A

Device B

Device C

Device D

CY2305

Implementation

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