ELECTRICAL SPECIFICATIONS
DCLK
(MHz)
-
6.25 - 135
Table 4-5. VGA RAMDAC Power Consumption
DAC mode
(State)
Shutdown
Active
PMax (mW)
VDD_DAC = 2.45V
VDD_DAC = 2.7V
0
0
150
180
Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
66
66 (x1)
66
100
100 (x1)
100
66
133 (x2)
66
66
133 (x2)
100
Mode
SYNC
SYNC
SYNC
ASYNC
DCLK
(MHz)
Stopped
135
Stopped
135
Stopped
135
Stopped
135
PMU
(State)
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
PMax (W)
V2.5V=2.45V
0.6
V2.5V=2.7V
0.9
1.4
1.8
0.9
1.2
1.7
2.3
0.8
1.1
1.5
2.0
1.5
1.9
2.1
2.7
0.7
0.9
1.7
2.1
0.9
1.2
1.9
2.5
0.8
1.1
1.6
2.1
1.5
1.9
2.3
2.9
Note 1: PCI clock at 33MHz
HCLK
(MHz)
66
100
66
66
Table 4-7. 3.3V Power Consumptions (VDD)
CPUCLK
(MHz)
66 (x1)
100 (x1)
133 (x2)
133 (x2)
MCLK
(MHz)
66
100
66
100
DCLK
(MHz)
6.26
135
6.26
135
6.26
135
6.26
135
PMU
(State)
Full Speed
Full Speed
Full Speed
Full Speed
PMax
(mW)
90
160
115
180
100
165
115
180
VDD_DCLK_PLL
VDD_DEVCLK_PLL
VDD_HCLKI_PLL
VDD_HCLKO_PLL
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_PCICLK_PLL
Table 4-8. PLL Power Consumptions
PLL name
PMax (mW)
VDD_PLL = 2.45V
VDD_PLL = 2.7V
5
10
5
10
5
10
5
10
5
10
5
10
5
10
Release 1.5 - January 29, 2002
35/93