STPCC4 View Datasheet(PDF) - STMicroelectronics
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STPCC4 Datasheet PDF : 93 Pages
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ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10 lists the AC characteristics
of the SDRAM interface.
Figure 4-5. SDRAM Timing Diagram
MCLKx
MCLKI
STPC.output
Tdelay
Thigh
Tcycle
Tlow
Toutput (max)
Toutput (min)
STPC.input
Thold
Tsetup
Table 4-10. SDRAM Bus AC Timing
Name Parameter
Tcycle MCLKI Cycle Time
Thigh MCLKI High Time
Tlow MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
Tdelay MCLKx to MCLKI delay
MCLKI to Outputs Valid
Toutput MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
Tsetup MD[63:0] setup to MCKLI
Thold MD[63:0] hold from MCKLI
Note: These timing are for a load of 50pF.
For correct operation, the programmable read
clock delay (RDCLK) must be activated for the
CRTC and the delay set to the minimum. This is
done by setting the Latch_CRTC_Data_In bit in
the SDRAM Controller register 0 and clear the
bits[3:0] in register 1.
Min Typ Max Unit
10
ns
4
ns
4
ns
1
ns
1
ns
-0.9
ns
5.2
7
ns
6.5
8.8
ns
6.5
8.8
ns
3.75
4.0
ns
1.3
2.5
ns
The PC133 memory is recommended to reach
100MHz operation.
40/93
Release 1.5 - January 29, 2002
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