Table 4.4. PCI Bus AC Timing
Name
t1
t2
t3
t4
t5
T6
T7
T8
T9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Parameter
PCI_CLKI to AD[31:0] valid
PCI_CLKI to FRAME# valid
PCI_CLKI to CBE#[3:0] valid
PCI_CLKI to PAR valid
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
PCI_CLKI to PCI_GNT# valid
AD[31:0] bus setup to PCI_CLKI
AD[31:0] bus hold from PCI_CLKI
PCI_REQ#[2:0] setup to PCI_CLKI
PCI_REQ#[2:0] hold from PCI_CLKI
CBE#[3:0] setup to PCI_CLKI
CBE#[3:0] hold to PCI_CLKI
IRDY# setup to PCI_CLKI
IRDY# hold to PCI_CLKI
FRAME# setup to PCI_CLKI
FRAME# hold from PCI_CLKI
Table 4.5. IDE Bus AC Timing
Name
t20
t21
Parameter
DD[15:0] setup to PIOR#/SIOR# falling
DD[15:0} hold to PIOR#/SIOR# falling
Table 4.6. SDRAM Bus AC Timing
Name Parameter
ELECTRICAL SPECIFICATIONS
Min
Max
Unit
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
12
ns
7
ns
0
ns
10
ns
0
ns
7
ns
0
ns
7
ns
0
ns
7
ns
0
ns
Min
Max
Unit
15
ns
12
ns
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.