STPCE1EDBC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STPCE1EDBC Datasheet PDF : 87 Pages
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Table 2-4. ISA / IDE Dynamic Multiplexing
ISA BUS
(ISAOE# = 0)
RMRTCCS#
KBCS#
RTCRW#
RTCDS#
SA[19:8]
LA[23]
LA[22]
SA[21]
SA[20]
LA[19:17]
IOCHRDY
IDE
(ISAOE# = 1)
DD[15]
DD[14]
DD[13]
DD[12]
DD[11:0]
SCS3#
SCS1#
PCS3#
PCS1#
DA[2:0]
DIORDY
PIN DESCRIPTION
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Table 2-5. ISA / Local Bus Pin Sharing
ISA / IPC
SD[15:0]
DREQ_MUX[1:0]
SMEMR#
MEMW#
BHE#
AEN
ALE
MEMR#
IOR#
IOW#
REF#
IOCHCK#
GPIOCS#
ZWS#
SA[7:4]
TC, DACK_ENC[2:0]
SA[3]
ISAOE#,SA[2:0]
DEV_CLK, RTCAS
IOCS16#, MASTER#
SMEMW#, MCS16#
LOCAL BUS
PD[15:0]
PA[21:20]
PA[19]
PA[18]
PA[17]
PA[16]
PA[15]
PA[14]
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7:4]
PA[3:0]
PRDY
IOCS#[3:0]
FCS#[1:0]
PRD#[1:0]
PWR#[1:0]
Signal Name
BASIC CLOCKS AND RESETS
XTALO
ISA_CLK
ISA_CLK2X, OSC14M
GPCLK
HCLK
PCI_CLKO
MEMORY CONTROLLER
MCLKO
CS#[3:1]
CS#[0]
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
SERR#
PCI_GNT#[2:0]
ISA BUS INTERFACE
Table 2-6. Signal value on Reset
SYSRSTI# active
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
14MHz
Low
7MHz
14MHz
24MHz
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
66MHz if asynchonous mode, HCLK speed if synchronized mode.
High
High
0x00
High
High
SDRAM init sequence:
Write Cycles
Input
0x0000
Low
Input
Input
Input
High
First prefetch cycles
when not in Local Bus mode.
Release 1.3 - January 29, 2002
21/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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