STPCE1EDBC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCE1EDBC

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

ELECTRICAL SPECIFICATIONS

Table 4-11. ISA Bus AC Timing

Name Parameter

Min

Max

41

SA[19:0] SBHE valid to IOCHRDY negated

41a Memory access to 16-bit ISA Slave

6T

41b Memory access to 8-bit ISA Slave

12T

41c I/O access to 16-bit ISA Slave

6T

41d I/O access to 8-bit ISA Slave

12T

42

SA[19:0] SBHE valid to read data valid

42b Memory access to 16-bit ISA Slave Standard cycle

4T

42e Memory access to 8-bit ISA Slave Standard cycle

10T

42h I/O access to 16-bit ISA Slave Standard cycle

4T

42l I/O access to 8-bit ISA Slave Standard cycle

10T

47

MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated

47a Memory access to 16-bit ISA Slave

2T

47b Memory access to 8-bit ISA Slave

5T

47c I/O access to 16-bit ISA Slave

2T

47d I/O access to 8-bit ISA Slave

5T

48

MEMR#, SMEMR#, IOR# asserted to read data valid

48b Memory access to 16-bit ISA Slave Standard Cycle

2T

48e Memory access to 8-bit ISA Slave Standard Cycle

5T

48h I/O access to 16-bit ISA Slave Standard Cycle

2T

48l I/O access to 8-bit ISA Slave Standard Cycle

5T

54

IOCHRDY asserted to read data valid

54a Memory access to 16-bit ISA Slave

1T(R)/2T(W)

54b Memory access to 8-bit ISA Slave

1T(R)/2T(W)

54c I/O access to 16-bit ISA Slave

1T(R)/2T(W)

54d I/O access to 8-bit ISA Slave

1T(R)/2T(W)

55a

IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#,

IOR#, IOW# negated

1T

55b

IOCHRY asserted to MEMR#, SMEMR# negated (refresh)

1T

56

IOCHRDY asserted to next ALE# asserted

2T

57

IOCHRDY asserted to SA[19:0], SBHE invalid

2T

58

MEMR#, IOR#, SMEMR# negated to read data invalid

0T

59

MEMR#, IOR#, SMEMR# negated to data bus float

0T

61

Write data before MEMW# asserted

61a Memory access to 16-bit ISA Slave

2T

61b

Memory access to 8-bit ISA Slave (Byte copy at end of

start)

2T

61

Write data before SMEMW# asserted

61c Memory access to 16-bit ISA Slave

2T

61d Memory access to 8-bit ISA Slave

2T

61

Write Data valid before IOW# asserted

61e I/O access to 16-bit ISA Slave

2T

61f I/O access to 8-bit ISA Slave

2T

64a

MEMW# negated to write data invalid - 16-bit

1T

64b

MEMW# negated to write data invalid - 8-bit

1T

64c

SMEMW# negated to write data invalid - 16-bit

1T

64d

SMEMW# negated to write data invalid - 8-bit

1T

Note: The signal numbering refers to Table 4-7

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Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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