STPCE1EDBC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCE1EDBC

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

DESIGN GUIDELINES

The figure below describes a complete

implementation of the external glue logic for DMA

Request time-multiplexing and DMA Acknowledge

demultiplexing. Like for the interrupt lines, this

logic can be simplified when only few DMA

channels are used in the application.

This glue logic is not needed in Local bus mode as

it does not support DMA transfers.

Figure 6-11. Typical DMA multiplexing and demultiplexing

ISA, Refresh

ISA, PIO

ISA, FDC

ISA, PIO

Slave DMAC

ISA

ISA

ISA

DRQ[0]

DRQ[1]

DRQ[2]

DRQ[3]

DRQ[4]

DRQ[5]

DRQ[6]

DRQ[7]

ISA_CLK2X

ISA_CLK

DMA_ENC[0]

DMA_ENC[1]

DMA_ENC[2]

74x153

1C0

1C1 1Y

1C2

1C3

2C0

2C1 2Y

2C2

2C3

A

B

1G 2G

74x138

Y0#

Y1#

Y2#

A Y3#

B Y4#

C Y5#

Y6#

Y7#

G1

G2A G2B

DREQ_MUX[0]

DREQ_MUX[1]

DACK0#

DACK1#

DACK2#

DACK3#

DACK5#

DACK6#

DACK7#

68/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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