STPCI01 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STPCI01 Datasheet PDF : 55 Pages
| |||
PIN DESCRIPTION
Table 3-2. Definition of Signal Pins
Signal Name
Dir
Description
Qty
BASIC CLOCKS AND RESETS
SYSRSTI#*
I
System Reset / Power good
1
SYSRSTO#*
O
Reset Output to System
1
XTALI
I
14.3MHz Crystal Input
1
XTALO
O
14.3MHz Crystal Output
1
PCI_CLKI*
I
33MHz PCI/CardBus Input Clock
1
PCI_CLKO
O
33MHz PCI/CardBus Output Clock
1
ISA_CLK, ISA_CLK2X
O
ISA Clock x1 and x2 (also Multiplexer Select Line For IPC)
2
CLK14M
O
ISA bus synchronisation clock
1
HCLK*
I/O
33 / 66MHz Host Clock (Test)
1
DEV_CLK*
O
24MHz Peripheral Clock
1
GCLK2X
I/O
80MHz Graphics Clock
1
DCLK
I/O
135MHz Dot Clock
1
VDD_xxx_PLL
Power Supply for PLL Clocks
MEMORY INTERFACE
MA[11:0]
I/O
Memory Address
12
RAS#[3:0]
O
Row Address Strobe
4
CAS#[7:0]
O
Column Address Strobe
8
MWE#
O
Write Enable
1
MD[63:0]
I/O
Memory Data
64
LOCAL BUS INTERFACE (COMBINED WITH ISA BUS )
PA[21:0]*
O
Address Bus [21:0]
22
PD[15:0]*
I/O
Data Bus [15:0]
16
PRDY#*
I
Ready
1
PWR#[1:0]*
O
Memory and I/O Write signals
2
PRD#[1:0]*
O
Memory and I/O Read signals
2
FCS#[1:0]*, IOCS#[3:0]*
O
Flash Memory and I/O Chip Select
6
ISA BUS INTERFACE (COMBINED WITH LOCAL BUS, PARALLEL PORT, SERIAL INTERFACE)
LA[23:17]*
O
Unlatched Address
7
SA[19:0]*
O
Latched Address
20
SD[15:0]*
I/O
Data Bus
16
IOCHRDY*
I
I/O Channel Ready
1
ALE*
O
Address Latch Enable
1
BHE#*
O
System Bus High Enable
1
MEMR#*, MEMW#*
I/O
Memory Read & Write
2
SMEMR#*, SMEMW#*
O
System Memory Read and Write
2
IOR#*, IOW#*
I/O
I/O Read and Write
2
MASTER#*
I
Add On Card Owns Bus
1
MCS16#*, IOCS16#*
I
Memory Chip Select 16, I/O Chip Select 16
2
REF#*
I
Refresh Cycle
1
AEN*
O
Address Enable
1
IOCHCK#*
I
I/O Channel Check (ISA)
1
RTCRW#*
O
RTC Read / Write#
1
RTCDS#*
O
RTC Data Strobe
1
RTCAS#*
O
RTC Address Strobe
1
18/55
Issue 1.1
Share Link: 