STPCI0166BTC3 View Datasheet(PDF) - STMicroelectronics
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STPCI0166BTC3 Datasheet PDF : 55 Pages
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ELECTRICAL SPECIFICATIONS
4.4 DC CHARACTERISTICS
Table 4-2. DC Characteristics
± Recommended Operating conditions : VDD = 3.3V 0.3V, Tcase = 0 to 100°C unless otherwise specified
Symbol
Parameter
VDD
PDD
HCLK
VDAC
VOL
VOH
VILD
Operating Voltage
Supply Power
Internal Clock
DAC Voltage Reference
Output Low Voltage
Output High Voltage
Input Low Voltage
VIHD Input High Voltage
ILK
CIN
COUT
CCLK
Input Leakage Current
Input Capacitance
Output Capacitance
Clock Capacitance
Test conditions
VDD = 3.3V, HCLK = 66Mhz
(Note 1)
ILoad =1.5 to 8mA depending of the pin
ILoad =-0.5 to -8mA depending of the pin
Except XTALI
XTALI
Except XTALI
XTALI
Input, I/O
(Note 2)
(Note 2)
(Note 2)
Min
3.0
1.215
2.4
-0.3
-0.3
2.1
2.35
-5
Typ
3.3
3.2
1.235
Max
3.6
3.9
80
1.255
0.5
0.8
0.5
VDD+0.3
VDD+0.3
5
Unit
V
W
Mhz
V
V
V
V
V
V
V
µA
pF
pF
pF
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not yet released.
Table 4-3. RAMDAC DC Specification
Symbol
Vref
INL
DNL
FS
FSR
LSB
Zero
Compare
Parameter
Voltage Reference
Integrated Non Linear Error
Differentiated Non Linear Error
Full Scale
Full Scale Range
Least Significant Byte Size
Zero Scale @ 7.5IRE Mode
DAC to DAC matching
Min
1.00V
-
-
-
14.00 mA
54uA
0.95mA
-
Nom
1.12V
-
-
-
16.50mA
63uA
1.44mA
-
Max
1.24V
2 lsb
1lsb
20mA
19.00 mA
72uA
1.90mA
+/- 5%
4.5 AC CHARACTERISTICS
Table 4-5 through Table 4-14 list the AC
characteristics including output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1. The rising clock edge reference level
VREF , and other reference levels are shown in
Table 4-4 below for the STPC Industrial. Input or
output signals must cross these levels during
testing.
Figure 4-1 shows output delay (A and B) and
input setup and hold times (C and D). Input setup
and hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
Issue 1.1
35/55
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