Product Preview
GS832218(B/C)/GS832236(B/C)/GS832272(C)
AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5 V
50Ω
30pF*
DQ
225Ω
VT = 1.25 V
* Distributed Test Jig Capacitance
5pF* 225Ω
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ and PE Input Current
FT, SCD, ZQ Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
Symbol
IIL
IIN1
IIN2
IOL
VOH2
VOH3
VOL
Test Conditions
VIN = 0 to VDD
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Min
–1 uA
–1 uA
–1 uA
–100 uA
–1 uA
–1 uA
1.7 V
2.4 V
—
Max
1 uA
1 uA
100 uA
1 uA
1 uA
1 uA
—
—
0.4 V
Rev: 1.00 10/2001
21/44
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.