CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
| |||
CL-PS7500FE
System-on-a-Chip for Internet Appliance
Table 22-4. DRAM Timing
Symbol Parameter
40 MHz
MIN MAX
56 MHz
MIN MAX
Units
tcasl
MEMCLK rising to nCAS[3:0] falling
12
12
ns
tcash
MEMCLK rising to nCAS[3:0] rising
11
11
ns
tds_dram Read DATA setup to MEMCLK rising
−5
−5
ns
tdh_dram
tcac_fp a
tcac_edo b
Read DATA hold from MEMCLK rising
nCAS falling to data latched
nCAS falling to data latched
16
16
ns
21
21
ns
25
25
ns
tda1
MEMCLK rising to write DATA valid
23
23
ns
tda2
MEMCLK rising to write DATA valid
33
33
ns
tda3
MEMCLK falling to write DATA valid
1.0t − 6 15 1.0t − 6 15
ns
twdh
Write DATA hold from MEMCLK rising
9
9
ns
trash
MEMCLK rising to nRAS[x] rising
11
11
ns
trasl
tra1 c
tra2 d
MEMCLK rising to nRAS[x] falling
MEMCLK rising to RA[11:0] valid (row address)
MEMCLK rising to RA[11:0] valid (row address)
13
13
ns
36
36
ns
23
23
ns
tca1
MEMCLK rising to RA[11:0] valid (column address)
15
15
ns
tca2
MEMCLK falling to RA[11:0] valid (column address)
14
14
ns
tcah
Column address, RA[11:0] valid from MEMCLK rising
12
12
ns
tnwel
tnweh e
MEMCLK rising to nWE falling
MEMCLK rising to nWE rising
12
12
ns
10
10
ns
tcas2l
MEMCLK falling to nCAS[3:0] falling
12
12
ns
tcas2h
trp f
MEMCLK falling to nCAS[3:0] rising
nRAS precharge time
12
12
ns
3
3
MEMCLKs
a Minimum nCAS access time for Fast Page mode DRAM across all conditions, with nCAS loading of ≤ 100 pF, when MEMCLK
= 32 MHz.
b Minimum nCAS access time for EDO DRAM across all conditions, with nCAS loading of 100 pF or less.
c CPU accesses.
d DMA accesses.
e nWE rising does not change while external nCAS signals are still low.
f The minimum nRAS precharge time can be extended to four cycles by setting bit 6 of the DRAMCTL register.
June 1997
ADVANCE DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
205
Share Link: 