CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
q The final bit selects between 3 and 4 MEMCLK cycles of minimum nRAS[x] precharge time, tRP
SELFREF allows direct forcing of the nRAS and nCAS outputs. The default state of each of these bits is
‘0’, allowing normal operation of the nRAS and nCAS outputs. But, when a bit is set high, the relevant
nCAS or nRAS output is immediately forced active (low).
REFCR controls the refresh rate for CAS-before-RAS refresh. There are four possible refresh periods
from 128–16 µs.
9.2.2 DRAM Address Multiplexing
The multiplexing of the DRAM address onto the RA[11:0] outputs is slightly different for 32- and 16-bit
modes. The DRAM address requested by the ARM or DMA controller must be shifted up by one bit in 16-
bit mode, to enable two locations to be accessed to read or write one 32-bit word. The row/column
address multiplexing arrangements are shown below, where the numbers in the table refer to the address
bits provided by the ARM or DMA controller.
32-bit-wide DRAM Bank
RA[11:0]
Row address
Column address
16-bit-wide DRAM Bank
11 10 9 8 7 6 5 4 3 2 1 0
24 22 19 18 17 16 15 14 13 12 11 10
25 23 21 20 9 8 7 6 5 4 3 2
RA[11:0]
11 10 9 8 7 6 5 4 3 2 1 0
Row address
Column address
23 21 18 17 16 15 14 13 12 11 10 9
24 22 20 19 8 7 6 5 4 3 2 •
q This bit is generated separately by DRAM controller to access each 16-bit half-word sequentially.
9.2.3 Selection Between 16- and 32-bit DRAM
76543210
XPRESSSS
The DRAMCR at address 0x032000D0 allows the width of each of the four DRAM banks to be defined
for CL-PS7500FE. On reset, all banks are defined as 32-bits wide, so if a 16-bit system is being used it
is necessary to program this register before any writes to DRAM occur. It is not possible to write to DRAM
in 16-bit mode and read back from the same bank in 32-bit mode, or vice versa.
S
Write
16- or 32-bit mode select, one for each bank
bit[3] bank 3 DRAM width
0
32-bit
1
16-bit
70
MEMORY SUBSYSTEMS
ADVANCE DATA BOOK v2.0
June 1997
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