Military 5.0V pASIC 1 Family
Symbol
tIN
tINI
High Drive Buffer
Parameter
High Drive Input Delay
High Drive Input,
Inverting Delay
Clock Drivers
Wired Together
1
2
3
4
1
2
3
4
Propagation Delays (ns) [4]
Fanout
12 24 48 72 96
5.3 6.7
4.5 6.6
5.3 6.2 7.2
5.4 6.2
5.7 7.2
4.6 6.8
5.5 6.4 7.4
5.6 6.4
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as spec-
ified in the Operating Range.
8-20
20
Preliminary