TDA9177 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
TDA9177 Datasheet PDF : 28 Pages
| |||
Philips Semiconductors
YUV transient improvement processor
Product specification
TDA9177
The envelope signal generated by the step improvement
processor modulates the peaking setting in order to
reduce the amount of peaking for large sine excursions
see Figs 7 and 8.
The coring setting controls the coring level in the peaking
path for rejection of high-frequency noise. All three
settings facilitate reduction of the impact of the sharpness
features, e.g. for noisy luminance signals.
An external noise detector and a user-preferred noise
algorithm are needed to make a fully automatic I2C-bus
controlled smart sharpness control.
An on-board, hard-wired smart sharpness algorithm can
be executed by driving pin SNC with the output of an
external noise detector. This pin, however, is active both in
I2C-bus and pin mode. Figures 13 and 14 illustrate the
impact of the noise control voltage at pin SNC on the user
settings.
Figure 15 shows the relationship between the feature
settings STEEP, COR, PEAK, LWC and their
corresponding pin voltages.
Chrominance compensation
The chrominance delay lines compensate for the delay of
the luminance signal in the step improvement processor,
to ensure a correct colour fit. No delay compensation will
be performed in the chrominance path for line-width
corrections in the luminance path.
Successive approximation ADC
Pins ADEXT1 and ADEXT2 are connected to a 6-bit
successive approximation ADC, via a multiplexer.
The multiplexer toggles between the inputs with each field.
For each field flyback, a conversion is started for either of
the two inputs and the result is stored in the corresponding
bus register, ADEXT1 or ADEXT2.
In this way, any analog, slowly varying signal can be given
access to the I2C-bus. If a register access conflict occurs,
the data of that register is made invalid by setting the flag
bit DV (Data Valid) to zero.
I2C-bus
At power up, the bit STB (standby) in the control register is
reset, to leave control to the pins. However, the I2C-bus is
at standby and responds if properly addressed. By setting
STB to logic 1, the control of all features is instead left to
the I2C-bus registers. The PDD bit (Power Down Detected)
in the status register is set each time an interruption of the
supply power occurs and is reset only by reading the
status register. A 3-bit identification code can also be read
from the status register, which can be used to
automatically configure the application by software.
The input control registers can be written sequentially by
the I2C-bus by the embedded automatic subaddress
increment feature or by addressing it directly. The output
control functions cannot be addressed separately.
Reading out the output control functions always starts at
subaddress 00 and all subsequent words are read out by
the automatic subaddress increment procedure. The I2C
address is 40H if pin 6 (ADR) is connected to ground and
E0H if pin 6 (ADR) is connected to pin 23 (Vref).
I2C-bus specification
Slave address
A6 A5 A4 A3 A2 A1 A0 R/W
ADR 1 ADR 0
0
0
0
X
Auto-increment mode available for subaddresses.
1997 Dec 01
6
Share Link: 