Z86E4016KSC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z86E4016KSC

Z8 4K OTP MICROCONTROLLER

Zilog 

Zilog

Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS-

compatible I/O port. These eight I/O lines can be config-

ured under software control as a nibble I/O port, or as an

address port for interfacing external memory. The input

buffers are Schmitt-triggered and nibble programmed. Ei-

ther nibble output that can be globally programmed as

push-pull or open-drain. Low EMI output buffers can be

globally programmed by the software. Port 0 can be placed

under handshake control. In Handshake Mode, Port 3

lines P32 and P35 are used as handshake control lines.

The handshake direction is determined by the configura-

tion (input or output) assigned to Port 0's upper nibble. The

lower nibble must have the same direction as the upper

nibble.

For external memory references, Port 0 provides address

bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-

ble) depending on the required address space. If the ad-

dress range requires 12 bits or less, the upper nibble of

Port 0 can be programmed independently as I/O while the

lower nibble is used for addressing. If one or both nibbles

are needed for I/O operation, they must be configured by

writing to the Port 0 mode register. In ROMless mode, after

a hardware reset, Port 0 is configured as address lines

A15-A8, and extended timing is set to accommodate slow

memory access. The initialization routine can include re-

configuration to eliminate this extended timing mode. In

ROM mode, Port 0 is defined as input after reset.

Port 0 can be set in the High-Impedance Mode if selected

as an address output state, along with Port 1 and the con-

trol signals /AS, /DS, and R//W (Figure 18).

Z86E30/E31/E40

Z8 4K OTP Microcontroller

1

DS97Z8X0500

PRELIMINARY

25

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