Z8018220ASC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018220ASC

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog 

Zilog

WR 7' Prime

D7 D6 D5 D4 D3 D2 D1 D0

PRELIMINARY

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Auto Tx Flag

Auto EOM Reset

Auto RTS Deactivation

Rx FIFO Int Level

DTR/REQ Timing Mode

Tx FIFO Int Level

Extended Read Enable

32-bit CRC Enable

Write Register 9

D7 D6 D5 D4 D3 D2 D1 D0

0 0 No Reset

0 1 Not used

1 0 Channel Reset

1 1 Force Hardware Reset

VIS

NV

DLC

MIE

Status High//Status Low

Software INTACK Enable

0 0 NRZ

0 1 NRZI

1 0 FM1 (Transition = 1)

1 1 FM0 (Transition = 0)

6-Bit//8-Bit Sync

Loop Mode

Abort//Flag On Underrun

Mark//Flag Idle

Go Active On Poll

CRC Preset I//O

Write Register 11

D7 D6 D5 D4 D3 D2 D1 D0

0 0 /TRxC Out = Xtal Output

0 1 /TRxC Out = Transmit Clock

1 0 /TRxC Out = BR Generator Output

1 1 /TRxC Out = DPLL Output

/TRxC O/I

0 0 Transmit Clock = /RTxC Pin

0 1 Transmit Clock = /TRxC Pin

1 0 Transmit Clock = BR Generator Output

1 1 Transmit Clock = DPLL Output

0 0 Receive Clock = /RTxC Pin

0 1 Receive Clock = /TRxC Pin

1 0 Receive Clock = BR Generator Output

1 1 Receive Clock = DPLL Output

/RTxC Xtal//No Xtal

Figure 52. Write Register Bit Functions (Continued)

DS971820600

PS009801-0301

3-53

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