PIC16F882-E/PTSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F882-E/PTSQTP

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16F882/883/884/886/887

TABLE 17-16: I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min. Max. Units

Conditions

100*

101*

102*

103*

90*

91*

106*

107*

92*

109*

110*

*

Note 1:

2:

THIGH Clock high time

100 kHz mode

4.0

—

s Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

s Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

—

TLOW Clock low time

100 kHz mode

4.7

—

s Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

s Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

—

TR

SDA and SCL rise 100 kHz mode

—

1000 ns

time

400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from

10-400 pF

TF

SDA and SCL fall 100 kHz mode

—

300 ns

time

400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from

10-400 pF

TSU:STA Start condition

100 kHz mode

4.7

—

s Only relevant for

setup time

400 kHz mode

0.6

—

s Repeated Start condition

THD:STA Start condition hold 100 kHz mode

4.0

—

s After this period the first

time

400 kHz mode

0.6

—

s clock pulse is generated

THD:DAT Data input hold time 100 kHz mode

0

—

ns

400 kHz mode

0

0.9 s

TSU:DAT Data input setup 100 kHz mode

250

—

ns (Note 2)

time

400 kHz mode

100

—

ns

TSU:STO Stop condition

100 kHz mode

4.7

—

s

setup time

400 kHz mode

0.6

—

s

TAA

Output valid from 100 kHz mode

clock

400 kHz mode

—

3500 ns (Note 1)

—

—

ns

TBUF

Bus free time

100 kHz mode

400 kHz mode

4.7

—

s Time the bus must be free

1.3

—

s before a new transmission

can start

CB

Bus capacitive loading

—

400 pF

These parameters are characterized but not tested.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the

requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I2C bus specification), before the SCL line is released.

 2006-2012 Microchip Technology Inc.

DS41291G-page 275

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