PIC16F882T-I/SSSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F882T-I/SSSQTP Datasheet PDF : 338 Pages
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PIC16F882/883/884/886/887
FIGURE 8-2:
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0>
2
C12IN0-
C12IN1-
C12IN2-
C12IN3-
0
1
MUX
2
3
C1R
C1IN+
FixedRef
CVREF
0
MUX
1
0
MUX
1
C1VREF
C1RSEL
C1POL
DQ
Q1 EN
C1ON(1)
DQ
Q3*RD_CM1CON0 EN
CL
Reset
To
Data Bus
RD_CM1CON0
Set C1IF
To PWM Logic
C1VIN- -
C1VIN+
C1
+
C1POL
C1OUT
C1OUT (to SR Latch)
Note 1:
2:
3:
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
FIGURE 8-3:
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2POL
DQ
Q1 EN
C2CH<1:0>
2
C12IN0-
C12IN1-
C12IN2-
C12IN3-
0
1
MUX
2
3
C2ON(1)
C2VIN-
C2VIN+ C2
DQ
Q3*RD_CM2CON0 EN
CL
Reset
C2OUT
C2SYNC
To
Data Bus
RD_CM2CON0
Set C2IF
C2R
C2IN+
FixedRef
CVREF
0
MUX
1
0
MUX
1
C2VREF
C2RSEL
C2POL
From Timer1
Clock
DQ
0
MUX
1
SYNCC2OUT
To Timer1 Gate, SR Latch,
PWM Logic, and other
peripherals
Note 1:
2:
3:
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
DS41291G-page 90
2006-2012 Microchip Technology Inc.
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