STA3818WTR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA3818WTR

STA3818W for PHILIPS 32PFL3017H/60 / VQFN48 (7x7mm)

STMicroelectronics 

STA381BW

10 Revision history

Revision history

Table 184. Document revision history

Date Revision

Changes

08-Jun-2011

1

Initial release

28-Jun-2011

2

Removed TQFP64 package option

02-Sep-2011

3

Added note to Figure 46, 47, 48, 49, 50, and

Section 8.2: Headphone and 2 Vrms line out, referencing AN3959

Updated names of pin 32 and 33 in Figure 1: Block diagram, Figure 2: Pin connections

20-Dec-2011

4

VQFN48 (top view) and Table 2: Pin list

Document promoted from preliminary to full datasheet

Added “VDD3V3CHP” to Table 3 and Table 5

Updated footnotes in Table 7

Updated register names to “SVUP” and “SVDN” for addresses 37 and 38 in Table 100

Updated text in Table 46 andTable 121: PWM speed mode

Updated 2.0 channels, two full-bridges (OCFG = 00) on page 121

17-Jan-2012

5

Updated 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) on

page 123

Updated high-pass filter in Table 152

Textual changes to formulas in Section 7.17: EQ soft volume configuration registers (addr

0x37 - 0x38)

20-Jun-2012

6

Added overvoltage protection threshold (VOV) to Table 7: Electrical specifications - power

section

Removed ECLE bit and sections concerning “Auto EAPD on clock loss” from datasheet

Updated Table 14: Default register map table: NEW MAP on page 45

Updated Table 100: I2C registers summary on page 106

Updated Section 6.32: Enhanced zero-detect mute and input level measurement

(address 0x61-0x65, 0x3F, 0x40, 0x6F) on page 97

Added Table 90: Manual threshold register 0x3F, 0x40 and 0x6F on page 98

03-Aug-2012 7 Added Section 6.36: Charge pump synchronization (address 0x70) on page 101

Added Table 98: Charge pump sync configuration bits on page 101

Updated Section 7.24: Enhanced zero-detect mute and input level measurement

(address 0x50-0x54, 0x2E, 0x2F and 0x5E) on page 158

Added Table 174: Manual threshold register 0x2E, 0x2F and 0x5E on page 160

Added Section 7.28: Charge pump synchronization (address 0x5F) on page 163

Added Table 180: Charge pump sync configuration bits on page 163

Added Section 3.6: Power-on/off sequence (added Figure 4 and Figure 5)

17-May-2013 8

Updated description of CHPRD bit in Table 98 and Table 180

DocID018835 Rev 8

173/174

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