Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FSMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FSMC_NOE
62/123
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
tv(A_NE)
tv(BL_NE)
Address
t h(A_NOE)
t h(BL_NOE)
tsu(Data_NOE)
tsu(Data_NE)
t h(Data_NE)
th(Data_NOE)
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
Data
FSMC_NADV(1)
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
ai14991B
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1.5 5THCLK + 2 ns
tv(NOE_NE) FSMC_NEx low to FSMC_NOE low
0.5
1.5
ns
tw(NOE)
FSMC_NOE low time
5THCLK – 1.5 5THCLK + 1.5 ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1.5
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
7
ns
th(A_NOE) Address hold time after FSMC_NOE high
0.1
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
0
ns
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0
ns
tsu(Data_NE) Data to FSMC_NEx high setup time
2THCLK + 25
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
2THCLK + 25
ns
th(Data_NOE) Data hold time after FSMC_NOE high
0
ns
th(Data_NE) Data hold time after FSMC_NEx high
0
ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
5
ns
tw(NADV)
FSMC_NADV low time
THCLK + 1.5 ns
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 7