STM32F103ZEH7 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F103ZEH7

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 36. Synchronous multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

Max Unit

tw(CLK)

FSMC_CLK period

27.7

ns

td(CLKL-NExL)

FSMC_CLK low to FSMC_Nex low (x = 0...2)

2

ns

td(CLKH-NExH)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

THCLK + 2

ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

4

ns

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

5

ns

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

0

ns

td(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) TCK + 2

ns

td(CLKL-NWEL)

FSMC_CLK low to FSMC_NWE low

1

ns

td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high

THCLK +1

ns

td(CLKL-ADV)

FSMC_CLK low to FSMC_AD[15:0] valid

12

ns

td(CLKL-ADIV)

FSMC_CLK low to FSMC_AD[15:0] invalid

3

ns

td(CLKL-Data)

FSMC_A/D[15:0] valid after FSMC_CLK low

6

ns

tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high

7

ns

th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high

2

ns

td(CLKL-NBLH)

FSMC_CLK low to FSMC_NBL high

1

ns

1. CL = 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

69/123

Share Link: