PIC16LF876AT-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF876AT-I/ML

28/40/44-Pin Enhanced Flash Microcontrollers

Microchip Technology 

PIC16F87X

2.2.2.6 PIE2 Register

The PIE2 register contains the individual enable bits for

the CCP2 peripheral interrupt, the SSP bus collision

interrupt, and the EEPROM write operation interrupt.

REGISTER 2-6:

PIE2 REGISTER (ADDRESS 8Dh)

U-0

R/W-0

U-0

— Reserved —

bit 7

R/W-0

EEIE

R/W-0

BCLIE

U-0

U-0

R/W-0

—

—

CCP2IE

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-1

bit 0

Unimplemented: Read as '0'

Reserved: Always maintain this bit clear

Unimplemented: Read as '0'

EEIE: EEPROM Write Operation Interrupt Enable

1 = Enable EE Write Interrupt

0 = Disable EE Write Interrupt

BCLIE: Bus Collision Interrupt Enable

1 = Enable Bus Collision Interrupt

0 = Disable Bus Collision Interrupt

Unimplemented: Read as '0'

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc.

DS30292C-page 23

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