TDA9209
11 - I2C REGISTER DESCRIPTION
Register Sub-addressed - I2C Table 1
Sub-address
Hex Dec
Register Names
POR Value
Max.
Value
Hex Dec Hex Dec
01 01 Contrast (CRT)
8-bit DAC
B4 180 FE 254
02 02 Brightness (BRT)
8-bit DAC
B4 180 FF 255
03 03 Drive 1 (DRV)
8-bit DAC
B4 180 FE 254
04 04 Drive 2 (DRV)
8-bit DAC
B4 180 FE 254
05 05 Drive 3 (DRV)
8-bit DAC
B4 180 FE 254
06 06 Output DC Level (DCL)
4-bit DAC
09 09 0F 15
07 07 OSD Contrast (OSD)
08 08 BPCP & OCL
09 09 Miscellaneous
4-bit DAC
Refer to the I2C table 2
Refer to the I2C table 3
09 09 0F 15
04 04
1C 28
0A 10 Cut Off Out 1 DC Level (Cut-off)
8-bit DAC
B4 180 FF 255
0B 11 Cut Off Out 2 DC Level (Cut-off)
8-bit DAC
B4 180 FF 255
0C 12 Cut Off Out 3 DC Level (Cut-off)
8-bit DAC
B4 180 FF 255
0D 13 Bandwidth Adjustment (BW)
4-bit DAC
07 07 0F 15
For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed.
For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06).
For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).
BPCP & OCL Register (R8) - I2C Table 2 (see also Figure12)
b7 b6 b5 b4 b3 b2 b1 b0
Func tion
0
0 Internal BPCP triggered by HSYNC
0
1 Internal BPCP triggered by BLK
0
0
Internal BPCP synchronized by the trailing edge
0
1
Internal BPCP synchronized by the leading edge
000
Internal BPCP Width = 0.33 µs
001
Internal BPCP Width = 0.66 µs
010
Internal BPCP Width = 1 µs
011
Internal BPCP Width = 1.33 µs
1
Internal BPCP = BPCP input (Pin 23)
0
Normal Operation
1
Reserved (Force BPCP to 1 in test)
0
Normal Operation
1
Reserved (Force OCL to 1 in test)
0
Internal OCL pulse triggered by BLK (pin 24)
1
Internal OCL pulse = Internal BPCP
POR Value
x
x
x
x
x
x
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