FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

SERIAL IRQ

The SMI is enabled onto the SMI frame of the

Serial IRQ via bit 6 of SMI Enable Register 2.

SERIAL INTERRUPTS

The FDC37B80x will support the serial interrupt

to transmit interrupt information to the host

system. The serial interrupt scheme adheres to

the Serial IRQ Specification for PCI Systems,

Version 6.0.

Timing Diagrams For IRQSER Cycle

PCICLK = 33MHz_IN pin

IRQSER = SIRQ pin

A) Start Frame timing with source sampled a low pulse on IRQ1

PCICLK

IRQSER

Drive Source

SL START FRAME

IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME

or

H

H

RT SRT SRT SRT

START1

IRQ1 Host Controller

None

IRQ1

None

H=Host Control

SL=Slave Control

S=Sample

R=Recovery

T=Turn-around

1) Start Frame pulse can be 4-8 clocks wide.

110

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