FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

DEFINITION

INDEX

Pin Multiplex

0xC0

Bit[0] Reserved

Controls

Bit[1] DMA 3 Select

Bit[2] Reserved

Default = 0x02 on

Bit[3] 8042 Select

Vcc POR

Bit[4] Reserved

Bit[5:7] Reserved

Force Disk Change

0xC1

Bit[0] Force Change 0

Default = 0x03 on

(R/W) Bit[7:1] Reserved

Vcc POR

Force Change[0] can be written to 1 but is not

clearable by software.

Force Change 0 is cleared on nSTEP and nDS0

Floppy Data Rate

Select Shadow

UART1 FIFO

Control Shadow

UART2 FIFO

Control Shadow

PME Control

Default = 0x00 on

VTR POR

0xC2

(R)

0xC3

0xC4

0xC5

(R/W)

DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND

Force Change 0) OR nDSKCHG

Bit[0] Data Rate Select 0

Bit[1] Data Rate Select 1

Bit[2] PRECOMP 0

Bit[3] PRECOMP 1

Bit[4] PRECOMP 2

Bit[5] Reserved

Bit[6] Power Down

Bit[7] Soft Reset

Bit[0] FIFO Enable

Bit[1] RCVR FIFO Reset

Bit[2] XMIT FIFO Reset

Bit[3] DMA Mode Select

Bit[5:4] Reserved

Bit[6] RCVR Trigger (LSB)

Bit[7] RCVR Trigger (MSB)

Bit[0] FIFO Enable

Bit[1] RCVR FIFO Reset

Bit[2] XMIT FIFO Reset

Bit[3] DMA Mode Select

Bit[5:4] Reserved

Bit[6] RCVR Trigger (LSB)

Bit[7] RCVR Trigger (MSB)

Bit[0] PME_En

= 0 nPME signal assertion is disabled (default)

= 1 Enables FDC37B80x to assert nPME signal

Bit[7:1] Reserved

PME_En is not affected by Vcc POR, SOFT RESET

or HARD RESET

STATE

C,R

C

C

C

151

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