FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

SMI Enable Register 2 (SMI_EN2)

Register Location: < PM1_BLK >+15h System I/O Space

Default Value: 00h on Vbat POR

Attribute: Read/Write

Size: 8-bits

NAME

SMI Enable

Register 2

Default = 0x00

on Vbat POR

DESCRIPTION

This register is used to enable the different interrupt sources onto the

group nSMI output, and the group nSMI output onto the nSMI GPI/O pin.

Unless otherwise noted,

1=Enable

0=Disable

Bit[0] EN_MINT

Bit[1] EN_KINT

Bit[2] EN_IRINT

Bit[3] EN_BINT

Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI

0=Do not route to nSMI

1=Enable routing to nSMI.

Bit [5] EN_CIR

Note: the PME status bit for CIR is used as the SMI status bit for CIR (see

PME Status Register).

Bit[6] EN_SMI_PME: Enable the group nSMI output into the PME

interface logic.

0= Group SMI output does not go to PME interface logic

1= Enable group SMI output to PME interface logic

Bit[7] EN_SMI: Enable the group nSMI output onto the nSMI pin or Serial

IRQ frame (IRQ2).

0=SMI pin floats

1=Enable group nSMI output onto nSMI pin or serial IRQ frame

Note: the selection of either the nSMI pin or serial IRQ frame is done via

bit 7 of the IRQ Mux Control Register (0xC0 in Logical Device 8).

165

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