CLOCK TIMING
CLOCKI
t1
t2
t2
FIGURE 16 - INPUT CLOCK TIMING
NAME
TABLE 95 - INPUT CLOCK TIMING
DESCRIPTION
MIN
t1 Clock Cycle Time for 14.318MHZ
t2 Clock High Time/Low Time for 14.318MHz
t1 Clock Cycle Time for 32KHZ
t2 Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
FIGURE 17 - RESET TIMING
TYP
70
35
31.25
16.53
MAX
5
UNITS
ns
ns
µs
µs
ns
t4
RESET_DRV
TABLE 96 - RESET TIMING
NAME
DESCRIPTION
MIN TYP MAX UNITS
t4 RESET width (Note 1)
1.5
µs
Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
233