FDC37B78X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37B78X
SMSC -> Microchip
FDC37B78X Datasheet PDF : 258 Pages
| |||
NAME
TABLE 104 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE TIMING
DESCRIPTION
MIN TYP MAX
t1 nIOW Asserted to PDATA Valid
0
50
t2 Command Deasserted to nWRITE Change
0
40
t3 nWRITE to Command
5
35
t4 nIOW Deasserted to Command Deasserted (Note 2)
50
t5 Command Deasserted to PDATA Invalid
50
t6 Time Out
10
12
t8 SDATA Valid to nIOW Asserted
10
t9 nIOW Deasserted to DATA Invalid
0
t10 nIOW Asserted to IOCHRDY Asserted
0
24
t11 nWAIT Deasserted to IOCHRDY Deasserted
40
t12 IOCHRDY Deasserted to nIOW Deasserted
10
t13 nIOW Asserted to nWRITE Asserted
0
50
t16 PDATA Valid to Command Asserted
10
35
t17 Ax Valid to nIOW Asserted
40
t18 nIOW Deasserted to Ax Invalid
10
t19 nIOW Deasserted to nIOW or nIOR Asserted
100
t20 nWAIT Asserted to IOCHRDY Deasserted
45
t21 Command Deasserted to nWAIT Deasserted
0
UNITS
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
Note 1 nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing
an EPP Write.
Note 2 The number is only valid if nWAIT is active when IOW goes active.
246
Share Link: 