FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

PDATA<7:0>

nACK

nAUTOFD

t2

t1

t5

t6

t4

t3

t4

FIGURE 29 - ECP PARALLEL PORT REVERSE TIMING

TABLE 108 - ECP PARALLEL PORT REVERSE TIMING

NAME

DESCRIPTION

MIN TYP MAX

t1 PDATA Valid to nACK Asserted

0

t2 nAUTOFD Deasserted to PDATA Changed

0

t3 nACK Asserted to nAUTOFD Deasserted

(Notes 1,2)

80

200

t4 nACK Deasserted to nAUTOFD Asserted (Note 2)

80

200

t5 nAUTOFD Asserted to nACK Asserted

0

t6 nAUTOFD Deasserted to nACK Deasserted

0

UNITS

ns

ns

ns

ns

ns

ns

Note 1

Note 2

Maximum value only applies if there is room in the FIFO and terminal count has not been

received. ECP can stall by keeping nAUTOFD low.

nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130

ns.

253

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