FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

An overrun or underrun will terminate the

current command and the transfer of data. Disk

writes will complete the current sector by

generating a 00 pattern and valid CRC. Reads

require the host to remove the remaining data

so that the result phase may be entered.

TABLE 15 - FIFO SERVICE DELAY

FIFO THRESHOLD

MAXIMUM DELAY TO SERVICING

EXAMPLES

AT 2 Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 4 µs - 1.5 µs = 2.5 µs

2 x 4 µs - 1.5 µs = 6.5 µs

8 x 4 µs - 1.5 µs = 30.5 µs

15 x 4 µs - 1.5 µs = 58.5 µs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING

AT 1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs

2 x 8 µs - 1.5 µs = 14.5 µs

8 x 8 µs - 1.5 µs = 62.5 µs

15 x 8 µs – 1.5 µs = 118.5 µs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING

AT 500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs

2 x 16 µs - 1.5 µs = 30.5 µs

8 x 16 µs - 1.5 µs = 126.5 µs

15 x 16 µs - 1.5 µs = 238.5 µs

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