SYMBOL
H/HDS
HLT
HUT
LOCK
MFM
NAME
Head Address
Head Load Time
Head Unload
Time
MFM/FM Mode
Selector
DESCRIPTION
Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector
ID field.
The time interval that FDC waits after loading the head and before
initializing a read or write operation. Refer to the Specify
command for actual delays.
The time interval from the end of the execution phase (of a read or
write command) until the head is unloaded. Refer to the Specify
command for actual delays.
Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters
of the CONFIGURE COMMAND can be reset to their default
values by a "software Reset". (A reset caused by writing to the
appropriate bits of either tha DSR or DOR)
A one selects the double density (MFM) mode. A zero selects
single density (FM) mode.
MT
N
NCN
ND
TABLE 21 - DESCRIPTION OF COMMAND SYMBOLS
Multi-Track
When set, this flag selects the multi-track operating mode. In this
Selector
mode, the FDC treats a complete cylinder under head 0 and 1 as
a single track. The FDC operates as this expanded track started
at the first sector under head 0 and ended at the last sector under
head 1. With this flag set, a multitrack read or write operation will
automatically continue to the first sector under head 1 when the
FDC finishes operating on the last sector under head 0.
Sector Size Code
This specifies the number of bytes in a sector. If this parameter is
"00", then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the "N'th" power) times 128. All values
up to "07" hex are allowable. "07"h would equal a sector size of
16k. It is the user's responsibility to not select combinations that
are not possible with the drive.
N Sector Size
New Cylinder
Number
0 128 Bytes
1 256 Bytes
2 512 Bytes
3 1024 Bytes
……
The desired cylinder number.
Non-DMA Mode
Flag
When set to 1, indicates that the FDC is to operate in the non-
DMA mode. In this mode, the host is interrupted for each data
transfer. When set to 0, the FDC operates in DMA mode,
interfacing to a DMA controller by means of the DRQ and nDACK
signals.
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