COM20022V-HT View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
COM20022V-HT Datasheet PDF : 88 Pages
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A0-A2
VALID
t1
t2
nCS
nRD
nWR
D0-D15
nIOCS16
t3
Note 3
t10
t6
t11
t5
t8
VALID DATA
VALID VALUE
t4
t9
Note 2
t7
t12
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
min
max units
t1 Address Setup to nRD Active
t2 Address Hold from nRD Inactive
t3 nCS Setup to nRD Active
t4 nCS Hold from nRD Inactive
t5 Cycle Time (nRD Low to Next Time Low)
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 nRD Low Width
t9 nRD High Width
t10 nWR to nRD Low
t11 nIOCS16 Output Delay from nCS Low
t12 nIOCS16 Hold Delay from nCS High
15
nS
10
nS
5**
nS
0
nS
4TARB*
nS
40** nS
0
20
nS
60
nS
20
nS
20
nS
40*** nS
0****
nS
* TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
*** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
**** t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 2:
!"#
% &
Note 3:
!"# +
&
' *(( ) &
FIGURE 20A - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
66
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