FDC37C932APM View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C932APM

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

DEFINITION

INDEX

SMI Enable

0xB5 R/W This register is used to enable the different interrupt

Register 2

sources onto the group nSMI output, and the group

nSMI output onto the nSMI GPI/O pin.

Default = 0x00

on VTR POR

Unless otherwise noted,

1=Enable

0=Disable

STATE

C

SMI Status

Register 1

Bit[0] EN_MINT

Bit[1] EN_KINT

Bit[2] EN_IRINT

Bit[3] EN_BINT

Bit[4] EN_P12: Enable 8042 P1.2 to route internally

to nSMI. 0=Do not route to nSMI, 1=Enable

routing to nSMI.

Bit[5] EN_ABINT: Access bus interrupt.

Bit[6] RTC_EN: This bit is used to enable the

setting of the RTC_STS bit to generate an SMI. The

RTC_STS bit is set anytime the RTC generates an

alarm 2.

Bit[7] EN_SMI: Enable the group nSMI output onto

the nSMI GPI/O pin. 0=SMI pin floats, 1=Enable

group nSMI output onto nSMI GPI/O pin.

0xB6 R/W This register is used to read the status of the SMI

C

inputs.

Default = 0x00

on VTR POR

The following bits must be cleared at their source.

Bit[0] IDE1 (IDEInterrupt)

Bit[1] PINT (Parallel Port Interrupt)

Bit[2] U2INT (UART 2 Interrupt)

Bit[3] U1INT (UART 1 Interrupt)

Bit[4] FINT (Floppy Disk Controller Interrupt)

Bit[5] GPINT2 (Group Interrupt 2)

Bit[6] GPINT1 (Group Interrupt 1)

Bit[7] WDT (Watch Dog Timer)

221

Share Link: