FDC37C93XAPM View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C93XAPM

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]

NAME

REG

DEFINITION

INDEX

SMI Status

0xB7 R/W This register is used to read the status of the SMI

Register 2

inputs.

Bit[0] MINT: Mouse Interrupt. Cleared at source.

Default = 0x00

Bit[1] KINT: Keyboard Interrupt. Cleared at source.

on VTR POR

Bit[2] IRINT: This bit is set by a transition on the IR

pin (RDX2 or GP12 as selected in CR L5-F1-B6 i.e.,

after the MUX). Cleared by a read of this register.

Bit[3] BINT: This bit is set when the DELAY counter

is started. Cleared by a read of this register.

Bit[4] P12: 8042 P1.2. Cleared at source

Bit[5] ABINT: Access Bus Interrupt. Cleared at

source.

Bit[6] RTC_STS: This bit is set when the RTC

generates an alarm 2. Additionally if the RTC_EN bit

is set then the setting of the RTC_STS bit will

generate an SMI. Cleared by writing a 1 to this

location. Writing a 0 has no effect.

Bit[7] Reserved

Delay 2 Time Set

0xB8 R/W This register is used to set Delay 2 (for Soft Power

Register

Management) to a value from 500 msec to 32 sec.

The default value is 500msec.

Default = 0x00

on VTR POR

Bit[5:0] The value of these bits correspond to the

delay time as follows:

000000= 500msec min to 510msec max

000001= 1sec min to 1.01sec max

000010= 1.5sec min to 1.51sec max

000011= 2sec min to 2.01sec max

...

111111 = 32sec min to 32.01sec max

STATE

C

C

Bit[7:6] Reserved

222

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